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225 lines
7.9 KiB
225 lines
7.9 KiB
/* byte_order.h */
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#ifndef BYTE_ORDER_H
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#define BYTE_ORDER_H
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#include "ustd.h"
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#include <stdlib.h>
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#if 0
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#if defined(__GLIBC__)
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# include <endian.h>
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#endif
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#endif
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#if defined(__FreeBSD__) || defined(__DragonFly__) || defined(__APPLE__)
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# include <sys/types.h>
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#elif defined (__NetBSD__) || defined(__OpenBSD__)
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# include <sys/param.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* if x86 compatible cpu */
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#if defined(i386) || defined(__i386__) || defined(__i486__) || \
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defined(__i586__) || defined(__i686__) || defined(__pentium__) || \
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defined(__pentiumpro__) || defined(__pentium4__) || \
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defined(__nocona__) || defined(prescott) || defined(__core2__) || \
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defined(__k6__) || defined(__k8__) || defined(__athlon__) || \
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defined(__amd64) || defined(__amd64__) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_IX86) || \
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defined(_M_AMD64) || defined(_M_IA64) || defined(_M_X64)
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/* detect if x86-64 instruction set is supported */
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# if defined(_LP64) || defined(__LP64__) || defined(__x86_64) || \
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defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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# define CPU_X64
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# else
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# define CPU_IA32
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# endif
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#endif
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#include <cm3p/kwiml/abi.h>
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#if KWIML_ABI_ENDIAN_ID == KWIML_ABI_ENDIAN_ID_LITTLE
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# define CPU_LITTLE_ENDIAN
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# define IS_BIG_ENDIAN 0
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# define IS_LITTLE_ENDIAN 1
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#elif KWIML_ABI_ENDIAN_ID == KWIML_ABI_ENDIAN_ID_BIG
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# define CPU_BIG_ENDIAN
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# define IS_BIG_ENDIAN 1
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# define IS_LITTLE_ENDIAN 0
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#endif
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#if 0
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#define RHASH_BYTE_ORDER_LE 1234
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#define RHASH_BYTE_ORDER_BE 4321
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#if (defined(__BYTE_ORDER) && defined(__LITTLE_ENDIAN) && __BYTE_ORDER == __LITTLE_ENDIAN) || \
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(defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_LE
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#elif (defined(__BYTE_ORDER) && defined(__BIG_ENDIAN) && __BYTE_ORDER == __BIG_ENDIAN) || \
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(defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_BE
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#elif defined(_BYTE_ORDER)
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# if defined(_LITTLE_ENDIAN) && (_BYTE_ORDER == _LITTLE_ENDIAN)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_LE
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# elif defined(_BIG_ENDIAN) && (_BYTE_ORDER == _BIG_ENDIAN)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_BE
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# endif
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#elif defined(__sun) && defined(_LITTLE_ENDIAN)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_LE
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#elif defined(__sun) && defined(_BIG_ENDIAN)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_BE
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#endif
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/* try detecting endianness by CPU */
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#ifdef RHASH_BYTE_ORDER
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#elif defined(CPU_IA32) || defined(CPU_X64) || defined(__ia64) || defined(__ia64__) || \
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defined(__alpha__) || defined(_M_ALPHA) || defined(vax) || defined(MIPSEL) || \
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defined(_ARM_) || defined(__arm__) || defined(_M_ARM64) || defined(_M_ARM64EC) || \
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defined(__loongarch64)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_LE
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#elif defined(__sparc) || defined(__sparc__) || defined(sparc) || \
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defined(_ARCH_PPC) || defined(_ARCH_PPC64) || defined(_POWER) || \
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defined(__POWERPC__) || defined(POWERPC) || defined(__powerpc) || \
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defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || \
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defined(__hpux) || defined(_MIPSEB) || defined(mc68000) || \
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defined(__s390__) || defined(__s390x__) || defined(sel) || defined(__hppa__)
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# define RHASH_BYTE_ORDER RHASH_BYTE_ORDER_BE
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#else
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# error "Can't detect CPU architechture"
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#endif
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#define IS_BIG_ENDIAN (RHASH_BYTE_ORDER == RHASH_BYTE_ORDER_BE)
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#define IS_LITTLE_ENDIAN (RHASH_BYTE_ORDER == RHASH_BYTE_ORDER_LE)
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#endif
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#ifndef __has_builtin
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# define __has_builtin(x) 0
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#endif
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#define IS_ALIGNED_32(p) (0 == (3 & (uintptr_t)(p)))
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#define IS_ALIGNED_64(p) (0 == (7 & (uintptr_t)(p)))
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#if defined(_MSC_VER)
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#define ALIGN_ATTR(n) __declspec(align(n))
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#elif defined(__GNUC__)
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#define ALIGN_ATTR(n) __attribute__((aligned (n)))
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#else
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#define ALIGN_ATTR(n) /* nothing */
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#endif
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#if defined(_MSC_VER) || defined(__BORLANDC__)
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#define I64(x) x##ui64
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#else
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#define I64(x) x##ULL
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#endif
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#if defined(_MSC_VER)
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#define RHASH_INLINE __inline
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#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
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#define RHASH_INLINE inline
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#elif defined(__GNUC__)
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#define RHASH_INLINE __inline__
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#else
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#define RHASH_INLINE
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#endif
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/* define rhash_ctz - count traling zero bits */
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#if (defined(__GNUC__) && __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)) || \
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(defined(__clang__) && __has_builtin(__builtin_ctz))
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/* GCC >= 3.4 or clang */
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# define rhash_ctz(x) __builtin_ctz(x)
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#else
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unsigned rhash_ctz(unsigned); /* define as function */
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#endif
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void rhash_swap_copy_str_to_u32(void* to, int index, const void* from, size_t length);
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void rhash_swap_copy_str_to_u64(void* to, int index, const void* from, size_t length);
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void rhash_swap_copy_u64_to_str(void* to, const void* from, size_t length);
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void rhash_u32_mem_swap(unsigned* p, int length_in_u32);
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/* bswap definitions */
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#if (defined(__GNUC__) && (__GNUC__ >= 4) && (__GNUC__ > 4 || __GNUC_MINOR__ >= 3)) || \
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(defined(__clang__) && __has_builtin(__builtin_bswap32) && __has_builtin(__builtin_bswap64))
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/* GCC >= 4.3 or clang */
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# define bswap_32(x) __builtin_bswap32(x)
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# define bswap_64(x) __builtin_bswap64(x)
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#elif (_MSC_VER > 1300) && (defined(CPU_IA32) || defined(CPU_X64)) /* MS VC */
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# define bswap_32(x) _byteswap_ulong((unsigned long)x)
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# define bswap_64(x) _byteswap_uint64((__int64)x)
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#else
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/* fallback to generic bswap definition */
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static RHASH_INLINE uint32_t bswap_32(uint32_t x)
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{
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# if defined(__GNUC__) && defined(CPU_IA32) && !defined(__i386__) && !defined(RHASH_NO_ASM)
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__asm("bswap\t%0" : "=r" (x) : "0" (x)); /* gcc x86 version */
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return x;
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# else
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x = ((x << 8) & 0xFF00FF00u) | ((x >> 8) & 0x00FF00FFu);
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return (x >> 16) | (x << 16);
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# endif
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}
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static RHASH_INLINE uint64_t bswap_64(uint64_t x)
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{
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union {
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uint64_t ll;
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uint32_t l[2];
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} w, r;
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w.ll = x;
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r.l[0] = bswap_32(w.l[1]);
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r.l[1] = bswap_32(w.l[0]);
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return r.ll;
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}
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#endif /* bswap definitions */
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#if IS_BIG_ENDIAN
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# define be2me_32(x) (x)
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# define be2me_64(x) (x)
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# define le2me_32(x) bswap_32(x)
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# define le2me_64(x) bswap_64(x)
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# define be32_copy(to, index, from, length) memcpy((char*)(to) + (index), (from), (length))
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# define le32_copy(to, index, from, length) rhash_swap_copy_str_to_u32((to), (index), (from), (length))
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# define be64_copy(to, index, from, length) memcpy((char*)(to) + (index), (from), (length))
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# define le64_copy(to, index, from, length) rhash_swap_copy_str_to_u64((to), (index), (from), (length))
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# define me64_to_be_str(to, from, length) memcpy((to), (from), (length))
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# define me64_to_le_str(to, from, length) rhash_swap_copy_u64_to_str((to), (from), (length))
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#else /* IS_BIG_ENDIAN */
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# define be2me_32(x) bswap_32(x)
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# define be2me_64(x) bswap_64(x)
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# define le2me_32(x) (x)
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# define le2me_64(x) (x)
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# define be32_copy(to, index, from, length) rhash_swap_copy_str_to_u32((to), (index), (from), (length))
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# define le32_copy(to, index, from, length) memcpy((char*)(to) + (index), (from), (length))
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# define be64_copy(to, index, from, length) rhash_swap_copy_str_to_u64((to), (index), (from), (length))
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# define le64_copy(to, index, from, length) memcpy((char*)(to) + (index), (from), (length))
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# define me64_to_be_str(to, from, length) rhash_swap_copy_u64_to_str((to), (from), (length))
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# define me64_to_le_str(to, from, length) memcpy((to), (from), (length))
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#endif /* IS_BIG_ENDIAN */
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/* ROTL/ROTR macros rotate a 32/64-bit word left/right by n bits */
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#define ROTL32(dword, n) ((dword) << (n) ^ ((dword) >> (32 - (n))))
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#define ROTR32(dword, n) ((dword) >> (n) ^ ((dword) << (32 - (n))))
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#define ROTL64(qword, n) ((qword) << (n) ^ ((qword) >> (64 - (n))))
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#define ROTR64(qword, n) ((qword) >> (n) ^ ((qword) << (64 - (n))))
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#define CPU_FEATURE_SSE4_2 (52)
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#if defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)) \
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&& (defined(CPU_X64) || defined(CPU_IA32))
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# define HAS_INTEL_CPUID
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int has_cpu_feature(unsigned feature_bit);
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#else
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# define has_cpu_feature(x) (0)
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#endif
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#ifdef __cplusplus
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} /* extern "C" */
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#endif /* __cplusplus */
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#endif /* BYTE_ORDER_H */
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